(a) Field of the Invention
The present invention relates to a thin film transistor array panel and a method for manufacturing the same, especially to a method for manufacturing a thin film transistor array panel with less number of photolithography steps.
(b) Description of the Related Art
A liquid crystal display (LCD) is one of the most popular flat panel displays (FPDs). An LCD has two panels having electrodes for generating electric fields and a liquid crystal layer interposed therebetween.
The transmittance of incident light is controlled by the intensity of the electric field applied to the liquid crystal layer.
In the most widely used liquid crystal display, the field-generating electrodes are formed at each of the two panels, and one of the panels has switching elements such as thin film transistors.
In general, a thin film transistor array panel is manufactured by photolithography using a plurality of photomasks, and five or six photolithography steps are used. Since the photolithography process is expensive, it is desirable to reduce the number of the photolithography steps. Even though manufacturing methods using only four photolithography steps have been suggested, these methods are not easy to accomplish.
A conventional method for manufacturing a thin film transistor array panel using four photolithography steps is disclosed in U.S. Pat. No. 5,478,766 and will now be described.
First, a gate wire of aluminum or aluminum alloy is formed on a substrate using a first mask. Then, a gate insulating layer, an amorphous silicon layer, an n+ amorphous silicon layer, and a metal layer are sequentially deposited. The metal layer, the n+ amorphous silicon, and the amorphous silicon layer are patterned by using a second mask. At this time, gate pads of the gate wire are covered only with the gate insulating layer. An indium tin oxide (ITO) is deposited and patterned by using a third mask. Then the portions of the ITO layer over the gate pads are removed. After the metal layer and the underlying n+ amorphous silicon layer are patterned using the patterned ITO layer as etch mask, a passivation layer is deposited. A thin film transistor array panel is completed by patterning the passivation layer and the gate insulating layer thereunder using a fourth mask, thereby removing the portion of the passivation layer and the gate insulating layer on the gate pads.
As a result, the gate pads of aluminum or aluminum alloy are exposed in the conventional manufacturing method of photolithography using four masks. However, aluminum and aluminum alloy is vulnerable to the external physical and chemical stimuli and get easily damaged, even though they have advantages of a low resistivity. To compensate this matter, the gate lines are formed having a multiple-layered structure or made of materials that can endure physical and chemical stimuli. However, the former method complicates the manufacturing process, and the latter has a problem of a high resistivity.